Referring to FIG. 1, a flow diagram of a method of manufacturing a doped region of a transistor according to the conventional art is shown. As depicted in FIG. 1, the process begins with various initial steps performed on a wafer, at step 105. The initial steps may include processes such as cleaning, etching, deposition, and the like.
Next at step 110, an oxide layer is formed on the substrate. Typically, the oxide can be formed by any well-known oxidation, deposition, or the like process. Next, at step 115 a polysilicon layer is deposited on the oxide layer. The polysilicon layer can be formed by any well-known deposition process, such as chemical vapor deposition (CVD), or the like.
Next, at step 120, a resist layer is formed on the polysilicon layer. The resist can be any well-known light-sensitive polymer. Next, at step 125, the resist layer is patterned. The resist can be patterned utilizing any well-known lithography process.
Next at step 130, the polysilicon layer is selectively etched to expose portions of the substrate. The polysilicon layer may be patterned by any well-known method, such as dry etching, ion etching, or the like.
Next at step 135, the patterned resist is then removed by applying a resist stripper, which causes the resist to swell and lose adhesion to the surface upon which it is applied.
Next, at step 140, the present embodiment selectively dopes the exposed portions of the substrate. The doping can be performed by any well-known diffusion, implant, or the like process. For example, source and drain regions are defined by openings in the patterned polysilicon layer. An impurity is then introduced into the exposed portions of the substrate utilizing a particle accelerator. In a N-channel implementation, the donor impurity may be phosphorus, arsenic, or the like, having an implanted concentration of approximately 5×1014-5×1015 atoms per cubic centimeter. In an P-channel implementation, the acceptor impurity may be boron, or the like, having an implanted concentration of approximately 5×1014-5×1015 atoms per cubic centimeter. Optionally, the doping may also be utilized to selectively dope the patterned polysilicon layer (e.g., gate and the like).
Finally, at step 145, fabrication proceeds with various subsequent processing steps. The subsequent steps may include processes such as deposition, etching, annealing, cleaning, polishing, metalization, passivation, and/or the like.
Referring now to FIG. 2, a section view of a partially fabricated transistor 200 according to the conventional art is shown. As depicted in FIG. 2, the transistor is fabricated in and about a substrate 205. The substrate may either be p-type or n-type semiconductor material, for n-channel or p-channel respectively.
A thin oxide layer 210 is formed upon the surface of the substrate 205. The oxide layer 210 is typically formed by oxidizing the surface of the substrate. For example, if the substrate material is silicon (Si) and the oxidizing agent is oxygen (O), an oxide layer of silicon dioxide (SiO2) is formed
A polysilicon layer 215 is then formed upon the thin oxide layer 210. The polysilicon layer can be formed by any well-known deposition process. The polysilicon layer is then patterned to form one or more structures, such as a gate, or the like. The patterned polysilicon layer can be formed by any well-known method, such as potolithography and selective etching.
One or more sources 220 and/or drains 225 are then formed by implanting an impurity 230 into the substrate that is left exposed by the patterned polysilicon layer 215. Typically the impurity implant results in a source 220 and/or drain 225 having a substantially uniform doping profile with a depth of approximately 0.1 μm. In a p-type substrate implementation, the doping of the source 220 and/or drain 225 is provided by an impurity 230 such as phosphorus, arsenic, or the like, having an implanted concentration of approximately 5×1014-5×1015 atoms per cubic centimeter. In an n-type substrate implementation, the doping of the source 220 and/or drain 225 is provided by an impurity 230 such as boron, or the like, having an implanted concentration of approximately 5×1014-5×1015 atoms per cubic centimeter.
The doping levels of the source and/or drain regions affect device resistances and capacitances. To reduce the resistance of the source, drain, bitline and/or contact between such, the doping level should be as high as practical. However, high doping levels result in degraded performance of short channel transistors. For example, heavily doped source and/or drain regions result in depletion regions at the source/substrate and/or drain/substrate junctions, which extend primarily into the lightly doped channel region of the substrate. Punch through occurs when the depletion regions of the source/substrate and the drain/substrate junctions meet. Punch through results in a relatively high source to drain leakage current. In the convention art, to avoid punch through the channel length is maintained at a longer length than current fabrication techniques make possible, which inhibits further scaling. Alternatively, the source and/or drain region doping is reduced. However, reducing the doping level results in a higher resistance of the source, drain, and/or bitline. In addition, the diffusion region of each source/substrate and/or drain/substrate junction also comprises a capacitance. The greater that doping level the larger the depletion region of the source/substrate and/or drain/substrate junction. Hence, the high doping concentration results in a high junction capacitance.
As described above, the convention art is problematic in that increasing the doping concentration, to decrease resistance, increases short channel effects. The conventional art is also problematic in that increasing the doping concentration, to decrease resistance, also increases junction capacitance. Thus, there is a need for an improved source and/or drain region providing for reduced short channel effects, reduced source and/or drain region resistance, and/or reduced depletion region capacitance.